产品详情
说明： 基于开发板制成的出租车计费器，适用于大学生的课程设计
(Based development board made of taxi meter for college curriculum design)
(Based development board made of taxi meter for college curriculum design)
文件列表：
chuzhuche
.........\FPGA_PROJECT1.PRJFPG,29113,2012-07-04
.........\FPGA_Project1.PrjFpgStructure,351,2012-07-04
.........\FPGA_Project1.SO,729600,2010-11-04
.........\History
.........\ProjectOutputs
.........\..............\$$code$$.vhd,1604,2012-06-25
.........\..............\$$temp0.vhd,1212,2012-06-25
.........\..............\Default - All Constraints
.........\..............\.........................\AND2S.EDN,1616,2004-04-13
.........\..............\.........................\CDIV256DC50.EDN,11604,2004-04-13
.........\..............\.........................\FPGA_PROJECT1.bfl,83,2012-07-04
.........\..............\.........................\fpga_project1.bgn,5106,2012-07-04
.........\..............\.........................\fpga_project1.bit,403016,2012-07-04
.........\..............\.........................\fpga_project1.bld,5554,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.edf,832841,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.FlwCmp,140,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.mof,1044,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.mpf,705,2012-07-04
.........\..............\.........................\fpga_project1.ncd,258893,2012-07-04
.........\..............\.........................\fpga_project1.ngd,622095,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.npl,215,2012-07-04
.........\..............\.........................\fpga_project1.pad,16404,2012-07-04
.........\..............\.........................\fpga_project1.par,6285,2012-07-04
.........\..............\.........................\fpga_project1.rbt,3425154,2012-07-04
.........\..............\.........................\fpga_project1.twr,4180,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.ucf,524,2012-07-04
.........\..............\.........................\fpga_project1.xpi,46,2012-07-04
.........\..............\.........................\FPGA_PROJECT1_BUILD.UCF,524,2012-07-04
.........\..............\.........................\fpga_project1_cclk.bgn,5118,2012-07-04
.........\..............\.........................\fpga_project1_cclk.bit,403016,2012-07-04
.........\..............\.........................\fpga_project1_cclk.rbt,3425154,2012-07-04
.........\..............\.........................\FPGA_PROJECT1_CoreGen.txt,0,2012-07-04
.........\..............\.........................\fpga_project1_map.mrp,22913,2012-07-04
.........\..............\.........................\fpga_project1_map.ncd,128502,2012-07-04
.........\..............\.........................\fpga_project1_map.ngm,1575864,2012-07-04
.........\..............\.........................\fpga_project1_map.pcf,1059,2012-07-04
.........\..............\.........................\fpga_project1_pad.csv,16408,2012-07-04
.........\..............\.........................\fpga_project1_pad.txt,70601,2012-07-04
.........\..............\.........................\FPGA_PROJECT1_Synth.log,4918,2012-07-04
.........\..............\.........................\IOBUF8B.VHD,894,2003-11-07
.........\..............\.........................\J16B_8B2.VHD,1056,2004-12-22
.........\..............\.........................\J8B_8S.VHD,871,2004-12-22
.........\..............\.........................\LCD16X2A.EDN,68987,2004-04-16
.........\..............\.........................\Sheet1.VHD,25003,2012-07-04
.........\..............\.........................\Status Report.Txt,132,2012-07-04
.........\..............\.........................\_blf
.........\..............\.........................\....\FPGA_PROJECT1_body.blf,11304,2012-07-04
.........\..............\.........................\....\FPGA_PROJECT1_header.blf,1220,2012-07-04
.........\..............\.........................\....\IOBUF8B_body.blf,1342,2012-07-04
.........\..............\.........................\....\IOBUF8B_header.blf,515,2012-07-04
.........\..............\.........................\....\JFQLCD_body.blf,26522,2012-07-04
.........\..............\.........................\....\JFQLCD_header.blf,1165,2012-07-04
.........\..............\.........................\....\JFQZMK_body.blf,230641,2012-07-04
.........\..............\.........................\....\JFQZMK_header.blf,981,2012-07-04
.........\..............\.........................\....\LessThan_32u_32u_body.blf,3372,2012-07-04
.........\..............\.........................\....\LessThan_32u_32u_header.blf,990,2012-07-04
.........\..............\.........................\_ngo
.........\..............\.........................\....\AND2S.ngo,843,2012-07-04
.........\..............\.........................\....\CDIV256DC50.ngo,3908,2012-07-04
.........\..............\.........................\....\fpga_project1.ngo,393863,2012-07-04
.........\..............\.........................\....\LCD16X2A.ngo,26228,2012-07-04
.........\..............\.........................\....\netlist.lst,585,2012-07-04
.........\..............\FPGA_PROJECT1.AL,64,2012-06-25
.........\..............\Sheet1.VHD,24362,2012-07-04
.........\..............\VHDL2.AN,41938,2012-06-25
.........\Sheet1 SCH ECO 2010-11-4 10-39-43.LOG,264,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 10-43-45.LOG,198,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 10-53-20.LOG,330,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-04-03.LOG,265,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-07-29.LOG,134,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-09-50.LOG,466,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-27-21.LOG,398,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 15-23-59.LOG,397,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 15-35-26.LOG,331,2010-11-04
.........\Sheet1.SchDoc,100352,2010-11-19
.........\Sheet1.SchDocPreview,74242,2012-06-27
.........\Test_jfqzmk.VHDTST,2842,2010-11-03
.........\Test_jfqzmk.VHDTSTPreview,81905,2012-06-27
.........\VHDL1.Vhd,8488,2012-07-04
.........\VHDL1.VhdPreview,127311,2012-06-27
.........\VHDL2.Vhd,3327,2010-11-03
.........\VHDL2.VhdPreview,88455,2012-06-27
.........\FPGA_PROJECT1.PRJFPG,29113,2012-07-04
.........\FPGA_Project1.PrjFpgStructure,351,2012-07-04
.........\FPGA_Project1.SO,729600,2010-11-04
.........\History
.........\ProjectOutputs
.........\..............\$$code$$.vhd,1604,2012-06-25
.........\..............\$$temp0.vhd,1212,2012-06-25
.........\..............\Default - All Constraints
.........\..............\.........................\AND2S.EDN,1616,2004-04-13
.........\..............\.........................\CDIV256DC50.EDN,11604,2004-04-13
.........\..............\.........................\FPGA_PROJECT1.bfl,83,2012-07-04
.........\..............\.........................\fpga_project1.bgn,5106,2012-07-04
.........\..............\.........................\fpga_project1.bit,403016,2012-07-04
.........\..............\.........................\fpga_project1.bld,5554,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.edf,832841,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.FlwCmp,140,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.mof,1044,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.mpf,705,2012-07-04
.........\..............\.........................\fpga_project1.ncd,258893,2012-07-04
.........\..............\.........................\fpga_project1.ngd,622095,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.npl,215,2012-07-04
.........\..............\.........................\fpga_project1.pad,16404,2012-07-04
.........\..............\.........................\fpga_project1.par,6285,2012-07-04
.........\..............\.........................\fpga_project1.rbt,3425154,2012-07-04
.........\..............\.........................\fpga_project1.twr,4180,2012-07-04
.........\..............\.........................\FPGA_PROJECT1.ucf,524,2012-07-04
.........\..............\.........................\fpga_project1.xpi,46,2012-07-04
.........\..............\.........................\FPGA_PROJECT1_BUILD.UCF,524,2012-07-04
.........\..............\.........................\fpga_project1_cclk.bgn,5118,2012-07-04
.........\..............\.........................\fpga_project1_cclk.bit,403016,2012-07-04
.........\..............\.........................\fpga_project1_cclk.rbt,3425154,2012-07-04
.........\..............\.........................\FPGA_PROJECT1_CoreGen.txt,0,2012-07-04
.........\..............\.........................\fpga_project1_map.mrp,22913,2012-07-04
.........\..............\.........................\fpga_project1_map.ncd,128502,2012-07-04
.........\..............\.........................\fpga_project1_map.ngm,1575864,2012-07-04
.........\..............\.........................\fpga_project1_map.pcf,1059,2012-07-04
.........\..............\.........................\fpga_project1_pad.csv,16408,2012-07-04
.........\..............\.........................\fpga_project1_pad.txt,70601,2012-07-04
.........\..............\.........................\FPGA_PROJECT1_Synth.log,4918,2012-07-04
.........\..............\.........................\IOBUF8B.VHD,894,2003-11-07
.........\..............\.........................\J16B_8B2.VHD,1056,2004-12-22
.........\..............\.........................\J8B_8S.VHD,871,2004-12-22
.........\..............\.........................\LCD16X2A.EDN,68987,2004-04-16
.........\..............\.........................\Sheet1.VHD,25003,2012-07-04
.........\..............\.........................\Status Report.Txt,132,2012-07-04
.........\..............\.........................\_blf
.........\..............\.........................\....\FPGA_PROJECT1_body.blf,11304,2012-07-04
.........\..............\.........................\....\FPGA_PROJECT1_header.blf,1220,2012-07-04
.........\..............\.........................\....\IOBUF8B_body.blf,1342,2012-07-04
.........\..............\.........................\....\IOBUF8B_header.blf,515,2012-07-04
.........\..............\.........................\....\JFQLCD_body.blf,26522,2012-07-04
.........\..............\.........................\....\JFQLCD_header.blf,1165,2012-07-04
.........\..............\.........................\....\JFQZMK_body.blf,230641,2012-07-04
.........\..............\.........................\....\JFQZMK_header.blf,981,2012-07-04
.........\..............\.........................\....\LessThan_32u_32u_body.blf,3372,2012-07-04
.........\..............\.........................\....\LessThan_32u_32u_header.blf,990,2012-07-04
.........\..............\.........................\_ngo
.........\..............\.........................\....\AND2S.ngo,843,2012-07-04
.........\..............\.........................\....\CDIV256DC50.ngo,3908,2012-07-04
.........\..............\.........................\....\fpga_project1.ngo,393863,2012-07-04
.........\..............\.........................\....\LCD16X2A.ngo,26228,2012-07-04
.........\..............\.........................\....\netlist.lst,585,2012-07-04
.........\..............\FPGA_PROJECT1.AL,64,2012-06-25
.........\..............\Sheet1.VHD,24362,2012-07-04
.........\..............\VHDL2.AN,41938,2012-06-25
.........\Sheet1 SCH ECO 2010-11-4 10-39-43.LOG,264,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 10-43-45.LOG,198,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 10-53-20.LOG,330,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-04-03.LOG,265,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-07-29.LOG,134,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-09-50.LOG,466,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 12-27-21.LOG,398,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 15-23-59.LOG,397,2010-11-04
.........\Sheet1 SCH ECO 2010-11-4 15-35-26.LOG,331,2010-11-04
.........\Sheet1.SchDoc,100352,2010-11-19
.........\Sheet1.SchDocPreview,74242,2012-06-27
.........\Test_jfqzmk.VHDTST,2842,2010-11-03
.........\Test_jfqzmk.VHDTSTPreview,81905,2012-06-27
.........\VHDL1.Vhd,8488,2012-07-04
.........\VHDL1.VhdPreview,127311,2012-06-27
.........\VHDL2.Vhd,3327,2010-11-03
.........\VHDL2.VhdPreview,88455,2012-06-27
