产品详情
说明： 实现4位乘法器的流水线操作计算，便于理解流水线
(The implementation of pipelined operation of 4 bit multiplier is convenient for understanding pipelining)
(The implementation of pipelined operation of 4 bit multiplier is convenient for understanding pipelining)
文件列表：
e55_mul_addtree
e55_mul_addtree\4浣嶆祦姘寸嚎涔樻硶鍣?docx
e55_mul_addtree\mul_addtree.v
e55_mul_addtree\sim
e55_mul_addtree\sim\tb_mul_addtree.cr.mti
e55_mul_addtree\sim\tb_mul_addtree.mpf
e55_mul_addtree\sim\tb_mul_addtree.v
e55_mul_addtree\sim\vish_stacktrace.vstf
e55_mul_addtree\sim\vsim.wlf
e55_mul_addtree\sim\work
e55_mul_addtree\sim\work\mul_addtree
e55_mul_addtree\sim\work\mul_addtree\verilog.asm64
e55_mul_addtree\sim\work\mul_addtree\verilog.rw64
e55_mul_addtree\sim\work\mul_addtree\_primary.dat
e55_mul_addtree\sim\work\mul_addtree\_primary.dbs
e55_mul_addtree\sim\work\mul_addtree\_primary.vhd
e55_mul_addtree\sim\work\tb_mul_addtree
e55_mul_addtree\sim\work\tb_mul_addtree\verilog.asm64
e55_mul_addtree\sim\work\tb_mul_addtree\verilog.rw64
e55_mul_addtree\sim\work\tb_mul_addtree\_primary.dat
e55_mul_addtree\sim\work\tb_mul_addtree\_primary.dbs
e55_mul_addtree\sim\work\tb_mul_addtree\_primary.vhd
e55_mul_addtree\sim\work\_info
e55_mul_addtree\sim\work\_temp
e55_mul_addtree\sim\work\_temp\vlog4h3yny
e55_mul_addtree\sim\work\_temp\vlog936jhn
e55_mul_addtree\sim\work\_temp\vlogdtnxg8
e55_mul_addtree\sim\work\_vmake
e55_mul_addtree\浠跨湡鍥?png
e55_mul_addtree\4浣嶆祦姘寸嚎涔樻硶鍣?docx
e55_mul_addtree\mul_addtree.v
e55_mul_addtree\sim
e55_mul_addtree\sim\tb_mul_addtree.cr.mti
e55_mul_addtree\sim\tb_mul_addtree.mpf
e55_mul_addtree\sim\tb_mul_addtree.v
e55_mul_addtree\sim\vish_stacktrace.vstf
e55_mul_addtree\sim\vsim.wlf
e55_mul_addtree\sim\work
e55_mul_addtree\sim\work\mul_addtree
e55_mul_addtree\sim\work\mul_addtree\verilog.asm64
e55_mul_addtree\sim\work\mul_addtree\verilog.rw64
e55_mul_addtree\sim\work\mul_addtree\_primary.dat
e55_mul_addtree\sim\work\mul_addtree\_primary.dbs
e55_mul_addtree\sim\work\mul_addtree\_primary.vhd
e55_mul_addtree\sim\work\tb_mul_addtree
e55_mul_addtree\sim\work\tb_mul_addtree\verilog.asm64
e55_mul_addtree\sim\work\tb_mul_addtree\verilog.rw64
e55_mul_addtree\sim\work\tb_mul_addtree\_primary.dat
e55_mul_addtree\sim\work\tb_mul_addtree\_primary.dbs
e55_mul_addtree\sim\work\tb_mul_addtree\_primary.vhd
e55_mul_addtree\sim\work\_info
e55_mul_addtree\sim\work\_temp
e55_mul_addtree\sim\work\_temp\vlog4h3yny
e55_mul_addtree\sim\work\_temp\vlog936jhn
e55_mul_addtree\sim\work\_temp\vlogdtnxg8
e55_mul_addtree\sim\work\_vmake
e55_mul_addtree\浠跨湡鍥?png
