产品详情
说明： 16位单周期处理器的verilog实现，简单易懂，对计算机的结构学习有帮助。
(16 single-cycle processor verilog implement, easy to understand, the structure of learning computer help.)
(16 single-cycle processor verilog implement, easy to understand, the structure of learning computer help.)
文件列表：
sccpu
.....\aludec.v,588,2015-05-07
.....\clk_divider.v,863,2015-05-07
.....\controller.v,874,2015-05-08
.....\cpu.v,6994,2015-05-08
.....\cpu_test.v,1728,2015-05-07
.....\data_mem.v,1103,2015-05-08
.....\instru_mem.v,2349,2015-05-08
.....\i_memory.v,2354,2015-05-07
.....\maindec.v,2806,2015-05-08
.....\seg7_controller.v,2205,2015-05-07
.....\top_module.v,1491,2015-05-08
.....\aludec.v,588,2015-05-07
.....\clk_divider.v,863,2015-05-07
.....\controller.v,874,2015-05-08
.....\cpu.v,6994,2015-05-08
.....\cpu_test.v,1728,2015-05-07
.....\data_mem.v,1103,2015-05-08
.....\instru_mem.v,2349,2015-05-08
.....\i_memory.v,2354,2015-05-07
.....\maindec.v,2806,2015-05-08
.....\seg7_controller.v,2205,2015-05-07
.....\top_module.v,1491,2015-05-08
