产品详情
说明： Quartus下开发Verilog编写的串口程序，主要包含串并互转模块等，通过RTL和时序仿真
(Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed)
(Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed)
文件列表：
uart
....\db
....\..\logic_util_heursitic.dat,6072,2013-12-16
....\..\prev_cmp_uart.qmsg,83062,2013-12-16
....\..\uart.ae.hdb,9852,2013-11-27
....\..\uart.amm.cdb,272,2013-12-16
....\..\uart.asm.qmsg,2214,2013-12-16
....\..\uart.asm.rdb,1383,2013-12-16
....\..\uart.asm_labs.ddb,14713,2013-12-16
....\..\uart.cbx.xml,86,2013-12-16
....\..\uart.cmp.bpm,675,2013-12-16
....\..\uart.cmp.cdb,21487,2013-12-16
....\..\uart.cmp.hdb,13195,2013-12-16
....\..\uart.cmp.kpt,204,2013-12-16
....\..\uart.cmp.logdb,4,2013-12-16
....\..\uart.cmp.rdb,21853,2013-12-16
....\..\uart.cmp0.ddb,92908,2013-12-16
....\..\uart.cmp1.ddb,91342,2013-12-16
....\..\uart.cmp2.ddb,45967,2013-12-16
....\..\uart.cmp_merge.kpt,208,2013-12-16
....\..\uart.db_info,153,2013-11-27
....\..\uart.eda.qmsg,3836,2013-12-16
....\..\uart.fit.qmsg,36819,2013-12-16
....\..\uart.hier_info,5788,2013-12-16
....\..\uart.hif,2171,2013-12-16
....\..\uart.idb.cdb,3001,2013-12-16
....\..\uart.lpc.html,1191,2013-12-16
....\..\uart.lpc.rdb,457,2013-12-16
....\..\uart.lpc.txt,1696,2013-12-16
....\..\uart.map.bpm,643,2013-12-16
....\..\uart.map.cdb,7204,2013-12-16
....\..\uart.map.hdb,12491,2013-12-16
....\..\uart.map.kpt,1980,2013-12-16
....\..\uart.map.logdb,4,2013-12-16
....\..\uart.map.qmsg,14616,2013-12-16
....\..\uart.map_bb.cdb,1127,2013-12-16
....\..\uart.map_bb.hdb,9348,2013-12-16
....\..\uart.map_bb.logdb,4,2013-12-16
....\..\uart.pre_map.cdb,13955,2013-12-16
....\..\uart.pre_map.hdb,12180,2013-12-16
....\..\uart.rpp.qmsg,1839,2013-11-28
....\..\uart.rtlv.hdb,12129,2013-12-16
....\..\uart.rtlv_sg.cdb,14180,2013-12-16
....\..\uart.rtlv_sg_swap.cdb,805,2013-12-16
....\..\uart.sgate.rvd,9844,2013-11-28
....\..\uart.sgate_sm.rvd,4444,2013-11-28
....\..\uart.sgdiff.cdb,8078,2013-12-16
....\..\uart.sgdiff.hdb,12219,2013-12-16
....\..\uart.sld_design_entry.sci,212,2013-12-16
....\..\uart.sld_design_entry_dsc.sci,212,2013-12-16
....\..\uart.smart_action.txt,8,2013-12-16
....\..\uart.smp_dump.txt,384,2013-12-16
....\..\uart.sta.qmsg,13614,2013-12-16
....\..\uart.sta.rdb,12560,2013-12-16
....\..\uart.sta_cmp.8_slow.tdb,18314,2013-12-16
....\..\uart.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd,1211775,2013-12-16
....\..\uart.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd,1218452,2013-12-16
....\..\uart.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd,1214360,2013-12-16
....\..\uart.syn_hier_info,0,2013-12-16
....\..\uart.tis_db_list.ddb,235,2013-12-16
....\..\uart.tmw_info,364,2013-12-16
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\uart.db_info,153,2013-11-27
....\..............\...................\uart.root_partition.cmp.cbp,201,2013-12-16
....\..............\...................\uart.root_partition.cmp.cdb,9711,2013-12-16
....\..............\...................\uart.root_partition.cmp.dfp,33,2013-12-16
....\..............\...................\uart.root_partition.cmp.hdb,12751,2013-12-16
....\..............\...................\uart.root_partition.cmp.kpt,208,2013-12-16
....\..............\...................\uart.root_partition.cmp.logdb,4,2013-12-16
....\..............\...................\uart.root_partition.cmp.rcfdb,9065,2013-12-16
....\..............\...................\uart.root_partition.cmp.re.rcfdb,10234,2013-12-16
....\..............\...................\uart.root_partition.map.cbp,198,2013-12-16
....\..............\...................\uart.root_partition.map.cdb,7094,2013-12-16
....\..............\...................\uart.root_partition.map.dpi,977,2013-12-16
....\..............\...................\uart.root_partition.map.hdb,12917,2013-12-16
....\..............\...................\uart.root_partition.map.kpt,1983,2013-12-16
....\..............\README,653,2013-11-27
....\simulation
....\..........\modelsim
....\..........\........\gate_work
....\..........\........\.........\uart_top
....\..........\........\.........\........\verilog.prw,36923,2013-12-16
....\..........\........\.........\........\verilog.psm,198976,2013-12-16
....\..........\........\.........\........\_primary.dat,40848,2013-12-16
....\..........\........\.........\........\_primary.dbs,89216,2013-12-16
....\..........\........\.........\........\_primary.vhd,369,2013-12-16
....\..........\........\.........\uart_top_t
....\..........\........\.........\..........\verilog.prw,1882,2013-12-16
....\..........\........\.........\..........\verilog.psm,8336,2013-12-16
....\..........\........\.........\..........\_primary.dat,749,2013-12-16
....\..........\........\.........\..........\_primary.dbs,1381,2013-12-16
....\..........\........\.........\..........\_primary.vhd,80,2013-12-16
....\..........\........\.........\_info,749,2013-12-16
....\..........\........\.........\_temp
....\..........\........\.........\_vmake,26,2013-12-16
....\..........\........\msim_transcript,2256,2013-12-16
....\..........\........\rtl_work
....\..........\........\........\uart_receiver
....\..........\........\........\.............\verilog.prw,4658,2013-11-27
....\db
....\..\logic_util_heursitic.dat,6072,2013-12-16
....\..\prev_cmp_uart.qmsg,83062,2013-12-16
....\..\uart.ae.hdb,9852,2013-11-27
....\..\uart.amm.cdb,272,2013-12-16
....\..\uart.asm.qmsg,2214,2013-12-16
....\..\uart.asm.rdb,1383,2013-12-16
....\..\uart.asm_labs.ddb,14713,2013-12-16
....\..\uart.cbx.xml,86,2013-12-16
....\..\uart.cmp.bpm,675,2013-12-16
....\..\uart.cmp.cdb,21487,2013-12-16
....\..\uart.cmp.hdb,13195,2013-12-16
....\..\uart.cmp.kpt,204,2013-12-16
....\..\uart.cmp.logdb,4,2013-12-16
....\..\uart.cmp.rdb,21853,2013-12-16
....\..\uart.cmp0.ddb,92908,2013-12-16
....\..\uart.cmp1.ddb,91342,2013-12-16
....\..\uart.cmp2.ddb,45967,2013-12-16
....\..\uart.cmp_merge.kpt,208,2013-12-16
....\..\uart.db_info,153,2013-11-27
....\..\uart.eda.qmsg,3836,2013-12-16
....\..\uart.fit.qmsg,36819,2013-12-16
....\..\uart.hier_info,5788,2013-12-16
....\..\uart.hif,2171,2013-12-16
....\..\uart.idb.cdb,3001,2013-12-16
....\..\uart.lpc.html,1191,2013-12-16
....\..\uart.lpc.rdb,457,2013-12-16
....\..\uart.lpc.txt,1696,2013-12-16
....\..\uart.map.bpm,643,2013-12-16
....\..\uart.map.cdb,7204,2013-12-16
....\..\uart.map.hdb,12491,2013-12-16
....\..\uart.map.kpt,1980,2013-12-16
....\..\uart.map.logdb,4,2013-12-16
....\..\uart.map.qmsg,14616,2013-12-16
....\..\uart.map_bb.cdb,1127,2013-12-16
....\..\uart.map_bb.hdb,9348,2013-12-16
....\..\uart.map_bb.logdb,4,2013-12-16
....\..\uart.pre_map.cdb,13955,2013-12-16
....\..\uart.pre_map.hdb,12180,2013-12-16
....\..\uart.rpp.qmsg,1839,2013-11-28
....\..\uart.rtlv.hdb,12129,2013-12-16
....\..\uart.rtlv_sg.cdb,14180,2013-12-16
....\..\uart.rtlv_sg_swap.cdb,805,2013-12-16
....\..\uart.sgate.rvd,9844,2013-11-28
....\..\uart.sgate_sm.rvd,4444,2013-11-28
....\..\uart.sgdiff.cdb,8078,2013-12-16
....\..\uart.sgdiff.hdb,12219,2013-12-16
....\..\uart.sld_design_entry.sci,212,2013-12-16
....\..\uart.sld_design_entry_dsc.sci,212,2013-12-16
....\..\uart.smart_action.txt,8,2013-12-16
....\..\uart.smp_dump.txt,384,2013-12-16
....\..\uart.sta.qmsg,13614,2013-12-16
....\..\uart.sta.rdb,12560,2013-12-16
....\..\uart.sta_cmp.8_slow.tdb,18314,2013-12-16
....\..\uart.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd,1211775,2013-12-16
....\..\uart.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd,1218452,2013-12-16
....\..\uart.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd,1214360,2013-12-16
....\..\uart.syn_hier_info,0,2013-12-16
....\..\uart.tis_db_list.ddb,235,2013-12-16
....\..\uart.tmw_info,364,2013-12-16
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\uart.db_info,153,2013-11-27
....\..............\...................\uart.root_partition.cmp.cbp,201,2013-12-16
....\..............\...................\uart.root_partition.cmp.cdb,9711,2013-12-16
....\..............\...................\uart.root_partition.cmp.dfp,33,2013-12-16
....\..............\...................\uart.root_partition.cmp.hdb,12751,2013-12-16
....\..............\...................\uart.root_partition.cmp.kpt,208,2013-12-16
....\..............\...................\uart.root_partition.cmp.logdb,4,2013-12-16
....\..............\...................\uart.root_partition.cmp.rcfdb,9065,2013-12-16
....\..............\...................\uart.root_partition.cmp.re.rcfdb,10234,2013-12-16
....\..............\...................\uart.root_partition.map.cbp,198,2013-12-16
....\..............\...................\uart.root_partition.map.cdb,7094,2013-12-16
....\..............\...................\uart.root_partition.map.dpi,977,2013-12-16
....\..............\...................\uart.root_partition.map.hdb,12917,2013-12-16
....\..............\...................\uart.root_partition.map.kpt,1983,2013-12-16
....\..............\README,653,2013-11-27
....\simulation
....\..........\modelsim
....\..........\........\gate_work
....\..........\........\.........\uart_top
....\..........\........\.........\........\verilog.prw,36923,2013-12-16
....\..........\........\.........\........\verilog.psm,198976,2013-12-16
....\..........\........\.........\........\_primary.dat,40848,2013-12-16
....\..........\........\.........\........\_primary.dbs,89216,2013-12-16
....\..........\........\.........\........\_primary.vhd,369,2013-12-16
....\..........\........\.........\uart_top_t
....\..........\........\.........\..........\verilog.prw,1882,2013-12-16
....\..........\........\.........\..........\verilog.psm,8336,2013-12-16
....\..........\........\.........\..........\_primary.dat,749,2013-12-16
....\..........\........\.........\..........\_primary.dbs,1381,2013-12-16
....\..........\........\.........\..........\_primary.vhd,80,2013-12-16
....\..........\........\.........\_info,749,2013-12-16
....\..........\........\.........\_temp
....\..........\........\.........\_vmake,26,2013-12-16
....\..........\........\msim_transcript,2256,2013-12-16
....\..........\........\rtl_work
....\..........\........\........\uart_receiver
....\..........\........\........\.............\verilog.prw,4658,2013-11-27
