产品详情
说明： 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）
(Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal))
(Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal))
文件列表：
5956447divider
..............\divider
..............\.......\divider.v
..............\.......\div_ctl.v
..............\.......\div_datapath.v
..............\.......\div_tb.v
..............\.......\read me.txt
..............\divider
..............\.......\divider.v
..............\.......\div_ctl.v
..............\.......\div_datapath.v
..............\.......\div_tb.v
..............\.......\read me.txt
